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Data Sheet
PIXEL INPUT/OUTPUT FORMATTING
The output section of the ADV7612 is highly flexible. The pixel
output bus can support up to 36-bit 4:4:4 YCrCb or 36-bit 4:4:4
RGB. The pixel data supports both single and double data rates
modes 1 . In SDR mode, a 16-/20-/24-bit 4:2:2 or 24-/30-/36-bit
ADV7612
PIXEL DATA OUTPUT MODES FEATURES
The output pixel port features include the following:
? 8-/10-/12-bit ITU-R BT.656 4:2:2 YCrCb with embedded
4:4:4 output is possible. In DDR mode, the pixel output port can
be configured in an 8-/10-/12-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB.
Bus rotation is supported. Table 5 to Table 8 outline the different
output formats that are supported. All output modes are controlled
via I 2 C.
?
?
?
time codes and/or HS, VS, and FIELD output signals
16-/20-/24-bit YCrCb with embedded time codes and/or
HS and VS/FIELD pin timing
24-/30-/36-bit YCrCb/RGB with embedded time codes
and/or HS and VS/FIELD pin timing
DDR 8-/10-/12-bit 4:2:2 YCrCb
1
DDR mode is only supported only up to 50 MHz (an equivalent to data rate
?
DDR 12-/24-/30-/36 bit 4:4:4 RGB
clocked 100 MHz clock in SDR mode).
Table 5. SDR 4:2:2 Output Modes
SDR 4:2:2
OP_FORMAT_SEL[7:0]
Pixel Output
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
0x0 1
8-Bit SDR
ITU-R BT.656
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
0x1
10-Bit SDR
ITU-R BT.656
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
0x2
12-Bit SDR
ITU-R BT.656
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y11, Cb11, Cr11
Y10, Cb10, Cr10
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
0x6
12-Bit SDR
ITU-R BT.656
Mode 1
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
Y11, Cb11, Cr11
Y10, Cb10, Cr10
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y2, Cb2, Cr2
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
0x0A
12-Bit SDR
ITU-R BT.656
Mode 2
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y11, Cb11, Cr11
Y10, Cb10, Cr10
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
1
Modes 0x00, 0x01, 0x02, 0x06 and 0x0A require additional writes to IO Map reg. 0x19[7:6]=2’b11 and IO Map reg.0x33[6]=1
Rev. E | Page 13 of 20
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